PCIe Gen6 CEM Connector & PCB Design Optimizations

Event Time

Originally Aired - Wednesday, February 1 8:00 AM - 8:45 AM Pacific Time (US & Canada); Tijuana

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Event Location

Location: Great America J


Event Information

Title: PCIe Gen6 CEM Connector & PCB Design Optimizations

Description:

The PCIe Gen6 channel data-rate of 64GT/s requires better mating connector, an AIC with shorter electrical length, better PCB material, and improved grounding. The Gen6 surface-mount connector mates with smaller gold finger to achieve loss and crosstalk targets at a higher frequency. The mating area between the Add-in Card and connector has a big impact on the overall SI performance of the connector. Reducing the signal pad length and width in the AIC serves as a major factor to improve the impedance match of the mating area which automatically improves the Return Loss, and Insertion Loss for the overall channel.

Type: Sponsored Session

Pass Type: 2-Day Pass, All Access Pass, Expo Pass


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